CHERI Alliance formed to promote memory security tech … but where’s Arm?

CHERI Alliance formed to promote memory security tech ... but where's Arm?

June 18, 2024 at 11:07AM

The CHERI Alliance, formed by tech organizations, aims to promote the adoption of memory access security technology. CHERI, a hardware-based solution, targets vulnerabilities, such as buffer overflows, to enhance application security efficiently. While the initial members exclude Arm, the alliance welcomes collaboration with industry and aims to drive broader adoption through awareness and collaboration efforts.

From the meeting notes, the following key points were derived:

1. The CHERI Alliance CIC has been formed by a group of technology organizations to promote industry adoption of security technology focused on memory access, particularly the CHERI or Capability Hardware Enhanced RISC Instructions architecture.

2. The goal is to drive the adoption of enhanced security, with initial members including the FreeBSD Foundation, Capabilities Limited, SCI Semiconductor, Codasip, lowRISC, and the University of Cambridge.

3. The CHERI technology aims to combat common vulnerabilities such as buffer overflows and the misuse of pointers via use-after-free errors by implementing fine-grained memory protections in CPU hardware.

4. The alliance is looking to include representatives from both industry and academia on its governing board to galvanize industry leaders, system developers, users, and security experts to promote CHERI as an efficient security standard.

5. Notably, chip designer Arm is absent from the initial members, despite its prior involvement in the development and promotion of CHERI.

6. The CHERI Alliance is ISA agnostic and plans to work on creating awareness, reaching common ground on specifications for CHERI implementation, providing a networking platform, and leveraging academic-industry partnerships to drive broader industry adoption.

7. There is a focus on RISC-V open ISA for the CHERI effort, as Codasip and lowRISC are both involved in RISC-V design work, and the University of Cambridge announced CHERI ISAv9, which replaces CHERI-MIPS with CHERI-RISC-V as the primary reference architecture.

The CHERI Alliance is set to formally launch in September and is currently accepting new member applications. Interested parties can contact the alliance for more information.

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