Codasip Donates Tools to Develop Memory-Safe Chips

October 24, 2024 at 08:17AM Codasip donated its RISC-V software development kit to the CHERI Alliance to enhance chip memory safety for developers. The SDK includes essential tools like a C/C++ compiler, emulator, and build system, aiming to facilitate CHERI technology adoption in securing hardware memory against vulnerabilities like buffer overflows. ### Meeting Takeaways: 1. … Read more

Memory Safety is Key to Preventing Hardware Hacks

August 9, 2024 at 08:33AM The 2018 Spectre and Meltdown vulnerabilities exposed computer memory as a target for hackers to inject code and steal data. To address this, Microsoft is transitioning system applications to the Rust programming language for memory safety, while chip makers established the CHERI Alliance to create secure hardware architecture. Challenges include … Read more

CHERI Alliance Aims to Secure Hardware Memory

June 20, 2024 at 09:18AM The CHERI Alliance, launching in September, aims to enhance chip security by isolating hardware and software to safeguard against cyberattacks, addressing memory vulnerabilities particularly prevalent in ARM processors. The consortium, involving entities like University of Cambridge and SRI International, focuses on fine-grained memory protection for ARM, MIPS, and RISC-V architectures. … Read more

CHERI Alliance formed to promote memory security tech … but where’s Arm?

June 18, 2024 at 11:07AM The CHERI Alliance, formed by tech organizations, aims to promote the adoption of memory access security technology. CHERI, a hardware-based solution, targets vulnerabilities, such as buffer overflows, to enhance application security efficiently. While the initial members exclude Arm, the alliance welcomes collaboration with industry and aims to drive broader adoption … Read more